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| TECHNICAL DATA IN74ACT299 8-Bit Bidirectional Universal Shift Register with Parallel I/O High-Speed Silicon-Gate CMOS The IN74ACT299 is identical in pinout to the LS/ALS299, HC/HCT299. The IN74ACT299 may be used as a level converter for interfacing TTL or NMOS outputs to High Speed CMOS inputs. The IN74ACT299 features a multiplexed parallel input/output data port to achieve full 8-bit handling in a 20 pin package. Due to the large output drive capability and the 3-state feature, this device is ideally suited for interface with bus lines in a bus-oriented system. Two Mode-Select inputs and two Output Enable inputs are used to choose the mode of operation as listed in the Function Table. Synchronous parallel loading is accomplished by taking both ModeSelect lines, S1 and S2, high. This places the outputs in the highimpedance state, which permits data applied to the data port to be clocked into the register. Reading out of the register can be accomplished when the outputs are enabled. The active-low asynchronous Reset overrides all other inputs. * TTL/NMOS Compatible Input Levels * Outputs Directly Interface to CMOS, NMOS, and TTL * Operating Voltage Range: 4.5 to 5.5 V * Low Input Current: 1.0 A; 0.1 A @ 25C * Outputs Source/Sink 24 mA ORDERING INFORMATION IN74ACT299N Plastic IN74ACT299DW SOIC TA = -40 to 85 C for all packages PIN ASSIGNMENT LOGIC DIAGRAM PIN 20=VCC PIN 10 = GND Rev. 00 IN74ACT299 MAXIMUM RATINGS* Symbol VCC VIN VOUT IIN IOUT ICC PD Tstg TL * Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Output Voltage (Referenced to GND) DC Input Current, per Pin DC Output Sink/Source Current, per Pin DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) Value -0.5 to +7.0 -0.5 to VCC +0.5 -0.5 to VCC +0.5 20 50 50 750 500 -65 to +150 260 Unit V V V mA mA mA mW C C Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/C from 65 to 125C SOIC Package: : - 7 mW/C from 65 to 125C RECOMMENDED OPERATING CONDITIONS Symbol VCC VIN, VOUT TJ TA IOH IOL tr, tf * Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) Junction Temperature (PDIP) Operating Temperature, All Package Types Output Current - High Output Current - Low Input Rise and Fall Time (except Schmitt Inputs) * Min 4.5 0 -40 Max 5.5 VCC 140 +85 -24 24 Unit V V C C mA mA ns/V VCC =4.5 V VCC =5.5 V 0 0 10 8.0 VIN from 0.8 V to 2.0 V This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND(VIN or VOUT)VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. Rev. 00 IN74ACT299 DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) VCC Symbol VIH VIL VOH Parameter Minimum HighLevel Input Voltage Maximum Low Level Input Voltage Minimum HighLevel Output Voltage Test Conditions VOUT= 0.1 V or VCC-0.1 V VOUT= 0.1 V or VCC-0.1 V IOUT -50 A VIN=VIH or VIL IOH=-24 mA IOH=-24 mA VOL Maximum LowLevel Output Voltage IOUT 50 A * * Guaranteed Limits 25 C 2.0 2.0 0.8 0.8 4.4 5.4 3.86 4.86 0.1 0.1 0.36 0.36 0.1 -40C to 85C 2.0 2.0 0.8 0.8 4.4 5.4 3.76 4.76 0.1 0.1 0.44 0.44 1.0 1.5 0.6 6.0 A mA A V Unit V V V V 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 5.5 5.5 5.5 VIN= VIH or VIL IOL=24 mA IOL=24 mA VIN=VCC or GND VIN=VCC - 2.1 V IIN ICCT IOZ Maximum Input Leakage Current Additional Max. ICC/Input Maximum ThreeState Leakage Current +Minimum Dynamic Output Current +Minimum Dynamic Output Current Maximum Quiescent Supply Current (per Package) VIN (OE)= VIH or VIL VIN =VCC or GND VOUT =VCC or GND VOLD=1.65 V Max VOHD=3.85 V Min VIN=VCC or GND IOLD IOHD ICC 5.5 5.5 5.5 8.0 75 -75 80 mA mA A * All outputs loaded; thresholds on input associated with output under test. +Maximum test duration 2.0 ms, one output loaded at a time. Rev. 00 IN74ACT299 AC ELECTRICAL CHARACTERISTICS (VCC=5.0 V 10%, CL=50pF,Input tr=tf=3.0 ns) Guaranteed Limits Symbol fmax tPLH tPHL tPLH tPHL tPHL tPHL tPZH tPZL tPHZ tPLZ CIN Parameter Maximum Clock Frequency (Figure 1) Propagation Delay, Clock to QA' or QH' (Figure 1) Propagation Delay, Clock to QA' or QH' (Figure 1) Propagation Delay, Clock to QA thru QH (Figure 1) Propagation Delay, Clock to QA thru QH (Figure 1) Propagation Delay, Reset to QA' or QH' (Figure 2) Propagation Delay, Reset to QA thru QH (Figure 2) Propagation Delay , OE1, OE2 to QA thru QH (Figure 3) Propagation Delay , OE1, OE2 to QA thru QH (Figure 3) Propagation Delay , OE1, OE2 to QA thru QH (Figure 3) Propagation Delay , OE1, OE2 to QA thru QH (Figure 3) Maximum Input Capacitance 25 C Min 120 4.0 4.0 4.5 5.0 4.0 4.0 2.5 2.0 2.0 2.5 4.5 12.5 13.5 12.5 15.0 15.0 14.5 12.0 12.0 12.5 11.5 Max -40C to 85C Min 110 3.0 3.5 4.5 4.5 4.0 3.5 1.5 1.5 2.0 2.0 4.5 14.0 15.0 13.5 16.5 18.0 17.5 13.0 13.5 13.5 12.5 Max MHz ns ns ns ns ns ns ns ns ns ns pF Unit Typical @25C,VCC=5.0 V CPD Power Dissipation Capacitance 170 pF TIMING REQUIREMENTS(VCC=5.0 V 10%, CL=50pF, Input tr=tf=3.0 ns) Guaranteed Limits Symbol tsu tsu tsu th th th trec tw tw Parameter Minimum Setup Time, Mode Select S1 or S2 to Clock (Figure 4) Minimum Setup Time, Data Inputs PA thru PH to Clock (Figure 4) Minimum Setup Time, Data Inputs SA, SH to Clock (Figure 4) Minimum Hold Time, Clock to Mode Select S1 or S2 (Figure 4) Minimum Hold Time, Clock to Data Inputs PA thru PH (Figure 4) Minimum Hold Time, Clock to Data Inputs SA, SH (Figure 4) Minimum Recovery Time, Reset Inactive to Clock (Figure 2) Minimum Pulse Width, Clock (Figure 1) Minimum Pulse Width, Reset (Figure 2) 25 C 5.0 4.0 4.5 1.0 1.0 1.0 1.5 4.0 3.5 -40C to 85C 5.5 4.5 5.0 1.0 1.0 1.0 1.5 4.5 3.5 Unit ns ns ns ns ns ns ns ns ns Rev. 00 IN74ACT299 FUNCTION TABLE Inputs Mode Reset Mode Select S2 Reset L L L Shift Right H H H Shift Left H H H Parallel Load Hold H H H H X L H L L L H H H H L L L S1 L X H H H H L L L H L L L Output Enables OE1 L L X H X L H X L X H X L OE2 L L X X H L X H L X X H L X X X X X X Clock Serial Inputs DA D H X X X D D D X X X X X X X X X X X X X D D D X X X X L L L L L L L L L L L L L L L L L L L D D D QB QB QB PA PA PA PA L L L QG QG QG D D D PH PH PH PH Response PA/ PB/ PC/ PD/ PE/ PF/ PG/ PH/ QA' QH' QA QB QC QD QE QF QG QH QA through QH=Z Shift Right: QA through QH=Z; F A; F A FB; etc DA Shift Right: QA through QH=Z; FA; FA FB; etc DA Shift Right: DA FA =QA; FB =QB; etc FA Shift Left: QA through QH=Z; F H; F H FG; etc DH Shift Left: QA through QH=Z; F H; F H FG; etc DH Shift Left: DH FH =QH; FG =QG; etc FH Parallel Load:PN FN Hold: QA through QH=Z; FN=FN Hold: QA through QH=Z; FN=FN Hold: QN =QH Z = high impedance D = data on serial input F = flip-flop (see Logic Diagram) When one or both output controls are high the eight input/output terminals are disabled to the highimpedance state; however, sequential operation or clearing of the register is not affected. Rev. 00 IN74ACT299 Figure 1. Switching Waveform Figure 2. Switching Waveform Figure 3. Switching Waveform Figure 4. Switching Waveform Rev. 00 IN74ACT299 EXPANDED LOGIC DIAGRAM Rev. 00 IN74ACT299 N SUFFIX PLASTIC DIP (MS - 001AD) A Dimension, mm 20 11 B 1 10 Symbol A B C MIN 24.89 6.1 MAX 26.92 7.11 5.33 F L D F 0.36 1.14 2.54 7.62 0 2.92 7.62 0.2 0.38 0.56 1.78 C -T- SEATING PLANE G H H J N G D 0.25 (0.010) M T K M J K L M N 10 3.81 8.26 0.36 NOTES: 1. Dimensions "A", "B" do not include mold flash or protrusions. Maximum mold flash or protrusions 0.25 mm (0.010) per side. D SUFFIX SOIC (MS - 013AC) A 20 11 Dimension, mm Symbol MIN 12.6 7.4 2.35 0.33 0.4 1.27 9.53 0 0.1 0.23 10 0.25 8 0.3 0.32 10.65 0.75 MAX 13 7.6 2.65 0.51 1.27 H B P A B 1 G 10 C R x 45 C D F -TD 0.25 (0.010) M T C M K SEATING PLANE J F M G H J K M P R NOTES: 1. Dimensions A and B do not include mold flash or protrusion. 2. Maximum mold flash or protrusion 0.15 mm (0.006) per side for A; for B 0.25 mm (0.010) per side. Rev. 00 |
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